DCDC_FORCE=DCDC_FORCE_0, SVSMHS=SVSMHS_0, SVMHOE=SVMHOE_0, VCORETRAN=VCORETRAN_0, SVSMHOFF=SVSMHOFF_0, SVMHOUTPOLAL=SVMHOUTPOLAL_0, SVSMHLP=SVSMHLP_0
Control 0 Register
| SVSMHOFF | SVSM high-side off 0 (SVSMHOFF_0): The SVSMH is on 1 (SVSMHOFF_1): The SVSMH is off |
| SVSMHLP | SVSM high-side low power normal performance mode 0 (SVSMHLP_0): Full performance mode. See the device-specific data sheet for response times. 1 (SVSMHLP_1): Low power normal performance mode in LPM3, LPM4, and LPMx.5, full performance in all other modes. See the device-specific data sheet for response times. |
| SVSMHS | Supply supervisor or monitor selection for the high-side 0 (SVSMHS_0): Configure as SVSH 1 (SVSMHS_1): Configure as SVMH |
| SVSMHTH | SVSM high-side reset voltage level |
| SVMHOE | SVSM high-side output enable 0 (SVMHOE_0): SVSMHIFG bit is not output 1 (SVMHOE_1): SVSMHIFG bit is output to the device SVMHOUT pin. The device-specific port logic must be configured accordingly |
| SVMHOUTPOLAL | SVMHOUT pin polarity active low 0 (SVMHOUTPOLAL_0): SVMHOUT is active high. An error condition is signaled by a 1 at the SVMHOUT pin 1 (SVMHOUTPOLAL_1): SVMHOUT is active low. An error condition is signaled by a 0 at the SVMHOUT pin |
| DCDC_FORCE | Force DC-DC regulator operation 0 (DCDC_FORCE_0): DC-DC regulator operation not forced. Automatic fail-safe mechanism switches the core voltage regulator from DC-DC to LDO when the supply voltage falls below the minimum supply voltage necessary for DC-DC operation. 1 (DCDC_FORCE_1): DC-DC regulator operation forced. Automatic fail-safe mechanism is disabled and device continues to operate out of DC-DC regulator. |
| VCORETRAN | Controls core voltage level transition time 0 (VCORETRAN_0): 32 s / 100 mV 1 (VCORETRAN_1): 64 s / 100 mV 2 (VCORETRAN_2): 128 s / 100 mV (default) 3 (VCORETRAN_3): 256 s / 100 mV |